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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-10-06 16:54:29 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-10-06 16:54:29 +0000 |
| commit | f3fb71bfd7d216733a64a2e5d47a4e9a48016f14 (patch) | |
| tree | 274410cbf8486d92361a206800aca98236df0ef1 /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | d5613debf99ce918145e1204df702ed502f5ac84 (diff) | |
This is suppose to work now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23644 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 557da82d1d..bb2162b480 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1822,7 +1822,6 @@ void AlphaISel::Select(SDOperand N) { } else { //ISD::TRUNCSTORE switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) { default: assert(0 && "unknown Type in store"); - case MVT::i1: //FIXME: DAG does not promote this load case MVT::i8: Opc = Alpha::STB; break; case MVT::i16: Opc = Alpha::STW; break; case MVT::i32: Opc = Alpha::STL; break; |