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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-28 18:14:47 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-28 18:14:47 +0000 |
| commit | 98169be50bbec4cd3406c7e6557c8661764f2a94 (patch) | |
| tree | 8269420c0d6f43a0afdae822fd30389f66dd1397 /lib/Target/Alpha/AlphaCodeEmitter.cpp | |
| parent | fe660397e14ecba84e792ada489f2bda7269b413 (diff) | |
support bsr, and more .td simplification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22543 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaCodeEmitter.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index 8bd87666b8..a4e9e03d91 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -180,6 +180,9 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { int Offset = 0; bool useGOT = false; switch (MI.getOpcode()) { + case Alpha::BSR: + Reloc = Alpha::reloc_bsr; + break; case Alpha::LDLr: case Alpha::LDQr: case Alpha::LDBUr: |