Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 98 insertions, 37 deletions

diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index 35d09fdac3..94c065e05c 100644
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -26,6 +26,104 @@ Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
   : ARMBaseInstrInfo(STI), RI(*this, STI) {
 }
 
+unsigned Thumb2InstrInfo::
+getUnindexedOpcode(unsigned Opc) const {
+  // FIXME
+  return 0;
+}
+
+unsigned Thumb2InstrInfo::
+getOpcode(ARMII::Op Op) const {
+  switch (Op) {
+  case ARMII::ADDri: return ARM::t2ADDri;
+  case ARMII::ADDrs: return ARM::t2ADDrs;
+  case ARMII::ADDrr: return ARM::t2ADDrr;
+  case ARMII::B: return ARM::t2B;
+  case ARMII::Bcc: return ARM::t2Bcc;
+  case ARMII::BR_JTr: return ARM::t2BR_JTr;
+  case ARMII::BR_JTm: return ARM::t2BR_JTm;
+  case ARMII::BR_JTadd: return ARM::t2BR_JTadd;
+  case ARMII::FCPYS: return ARM::FCPYS;
+  case ARMII::FCPYD: return ARM::FCPYD;
+  case ARMII::FLDD: return ARM::FLDD;
+  case ARMII::FLDS: return ARM::FLDS;
+  case ARMII::FSTD: return ARM::FSTD;
+  case ARMII::FSTS: return ARM::FSTS;
+  case ARMII::LDR: return ARM::LDR;   // FIXME
+  case ARMII::MOVr: return ARM::t2MOVr;
+  case ARMII::STR: return ARM::STR;   // FIXME
+  case ARMII::SUBri: return ARM::t2SUBri;
+  case ARMII::SUBrs: return ARM::t2SUBrs;
+  case ARMII::SUBrr: return ARM::t2SUBrr;
+  case ARMII::VMOVD: return ARM::VMOVD;
+  case ARMII::VMOVQ: return ARM::VMOVQ;
+  default:
+    break;
+  }
+
+  return 0;
+}
+
+bool
+Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
+  if (MBB.empty()) return false;
+
+  // FIXME
+  switch (MBB.back().getOpcode()) {
+    //case ARM::t2BX_RET:
+    //  case ARM::LDM_RET:
+  case ARM::t2B:        // Uncond branch.
+  case ARM::t2BR_JTr:   // Jumptable branch.
+  case ARM::t2BR_JTm:   // Jumptable branch through mem.
+  case ARM::t2BR_JTadd: // Jumptable branch add to pc.
+    return true;
+  case ARM::tBX_RET:
+  case ARM::tBX_RET_vararg:
+  case ARM::tPOP_RET:
+  case ARM::tB:
+  case ARM::tBR_JTr:
+    return true;
+  default:
+    break;
+  }
+
+  return false;
+}
+
+
+bool Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+                                   MachineBasicBlock::iterator I,
+                                   unsigned DestReg, unsigned SrcReg,
+                                   const TargetRegisterClass *DestRC,
+                                   const TargetRegisterClass *SrcRC) const {
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (I != MBB.end()) DL = I->getDebugLoc();
+
+  if (DestRC == ARM::GPRRegisterClass) {
+    if (SrcRC == ARM::GPRRegisterClass) {
+      return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
+    } else if (SrcRC == ARM::tGPRRegisterClass) {
+      BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
+      return true;
+    }
+  } else if (DestRC == ARM::tGPRRegisterClass) {
+    if (SrcRC == ARM::GPRRegisterClass) {
+      BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
+      return true;
+    } else if (SrcRC == ARM::tGPRRegisterClass) {
+      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
+      return true;
+    }
+  }
+
+  return false;
+}
+
+
+
+
+
+
 bool Thumb2InstrInfo::isMoveInstr(const MachineInstr &MI,
                                   unsigned &SrcReg, unsigned &DstReg,
                                   unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
@@ -35,7 +133,6 @@ bool Thumb2InstrInfo::isMoveInstr(const MachineInstr &MI,
   switch (oc) {
   default:
     return false;
-  // FIXME: Thumb2
   case ARM::tMOVr:
   case ARM::tMOVhir2lor:
   case ARM::tMOVlor2hir:
@@ -54,7 +151,6 @@ unsigned Thumb2InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
                                               int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
-  // FIXME: Thumb2
   case ARM::tRestore:
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isImm() &&
@@ -71,7 +167,6 @@ unsigned Thumb2InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
                                              int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
-  // FIXME: Thumb2
   case ARM::tSpill:
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isImm() &&
@@ -84,36 +179,6 @@ unsigned Thumb2InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
   return 0;
 }
 
-bool Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator I,
-                                   unsigned DestReg, unsigned SrcReg,
-                                   const TargetRegisterClass *DestRC,
-                                   const TargetRegisterClass *SrcRC) const {
-  DebugLoc DL = DebugLoc::getUnknownLoc();
-  if (I != MBB.end()) DL = I->getDebugLoc();
-
-  // FIXME: Thumb2
-  if (DestRC == ARM::GPRRegisterClass) {
-    if (SrcRC == ARM::GPRRegisterClass) {
-      BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
-      return true;
-    } else if (SrcRC == ARM::tGPRRegisterClass) {
-      BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
-      return true;
-    }
-  } else if (DestRC == ARM::tGPRRegisterClass) {
-    if (SrcRC == ARM::GPRRegisterClass) {
-      BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
-      return true;
-    } else if (SrcRC == ARM::tGPRRegisterClass) {
-      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
-      return true;
-    }
-  }
-
-  return false;
-}
-
 bool Thumb2InstrInfo::
 canFoldMemoryOperand(const MachineInstr *MI,
                      const SmallVectorImpl<unsigned> &Ops) const {
@@ -154,7 +219,6 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 
   assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
 
-  // FIXME: Thumb2
   if (RC == ARM::tGPRRegisterClass) {
     BuildMI(MBB, I, DL, get(ARM::tSpill))
       .addReg(SrcReg, getKillRegState(isKill))
@@ -170,7 +234,6 @@ void Thumb2InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
   DebugLoc DL = DebugLoc::getUnknownLoc();
   unsigned Opc = 0;
 
-  // FIXME: Thumb2. Is GPRRegClass here correct?
   assert(RC == ARM::GPRRegisterClass && "Unknown regclass!");
   if (RC == ARM::GPRRegisterClass) {
     Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
@@ -191,7 +254,6 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  // FIXME: Thumb2
   assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
 
   if (RC == ARM::tGPRRegisterClass) {
@@ -208,7 +270,6 @@ loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
   DebugLoc DL = DebugLoc::getUnknownLoc();
   unsigned Opc = 0;
 
-  // FIXME: Thumb2. Is GPRRegClass ok here?
   if (RC == ARM::GPRRegisterClass) {
     Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
   }