diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-04 23:39:08 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-04 23:39:08 +0000 |
| commit | 670a456c8323fc5da4752bdcf2b416ebef1bc66c (patch) | |
| tree | 7b87aa48204e285f189ff1dcaedd559d82aee4c3 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.h | |
| parent | b572830a52faad2fffc7119de53aa96c18d9bf07 (diff) | |
RFE encoding should also specify the "should be" encoding bits.
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE
Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.h')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h index 9c30d332d1..56dd85a7d9 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h @@ -141,6 +141,12 @@ static inline bool isUnaryDP(uint64_t TSFlags) { return (TSFlags & ARMII::UnaryDP); } +/// A NEON Domain instruction has cond field (Inst{31-28}) as 0b1111. +static inline bool isNEONDomain(uint64_t TSFlags) { + return (TSFlags & ARMII::DomainNEON) || + (TSFlags & ARMII::DomainNEONA8); +} + /// This four-bit field describes the addressing mode used. /// See also ARMBaseInstrInfo.h. static inline unsigned getAddrMode(uint64_t TSFlags) { |