diff options
| author | Jim Grosbach <grosbach@apple.com> | 2011-07-29 20:26:09 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-29 20:26:09 +0000 |
| commit | e1cf5902ec832cecdd5a94b9701930253d410741 (patch) | |
| tree | e052669ed3277aa0c729b28f73e9a04b9a105cad /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | |
| parent | c91d6263cf3c7d4f211f5b95c7b4dd822435c300 (diff) | |
ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 983589f698..8b22786843 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -798,7 +798,7 @@ static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn, // MSR/MSRsys: Rm mask=Inst{19-16} // BXJ: Rm // MSRi/MSRsysi: so_imm -// SRSW/SRS: ldstm_mode:$amode mode_imm +// SRS: mode_imm // RFE: Rn static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { @@ -858,15 +858,12 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, NumOpsAdded = 2; return true; } - if (Opcode == ARM::SRSW || Opcode == ARM::SRS) { - ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn)); - MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode))); - - if (Opcode == ARM::SRSW || Opcode == ARM::SRS) - MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, - decodeRn(insn)))); - NumOpsAdded = 3; + if (Opcode == ARM::SRSDA || Opcode == ARM::SRSDB || + Opcode == ARM::SRSIA || Opcode == ARM::SRSIB || + Opcode == ARM::SRSDA_UPD || Opcode == ARM::SRSDB_UPD || + Opcode == ARM::SRSIA_UPD || Opcode == ARM::SRSIB_UPD) { + MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); + NumOpsAdded = 1; return true; } if (Opcode == ARM::RFEDA || Opcode == ARM::RFEDB || |