diff options
| author | Jim Grosbach <grosbach@apple.com> | 2011-11-29 22:58:48 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-29 22:58:48 +0000 |
| commit | 4c7edb3ad8bd513c59190f6ebee9bee34af7d247 (patch) | |
| tree | d8750e89dc9d24fb67192f7fae538f9fbe0cda1c /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 2662c83a594b5df8deef2a540595a5faa72cfbdc (diff) | |
ARM assembly parsing and encoding for four-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 36 |
1 files changed, 8 insertions, 28 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 69f4b261ad..fb96407929 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2204,10 +2204,14 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST1d16Twb_register: case ARM::VST1d32Twb_register: case ARM::VST1d64Twb_register: - case ARM::VST1d8Q_UPD: - case ARM::VST1d16Q_UPD: - case ARM::VST1d32Q_UPD: - case ARM::VST1d64Q_UPD: + case ARM::VST1d8Qwb_fixed: + case ARM::VST1d16Qwb_fixed: + case ARM::VST1d32Qwb_fixed: + case ARM::VST1d64Qwb_fixed: + case ARM::VST1d8Qwb_register: + case ARM::VST1d16Qwb_register: + case ARM::VST1d32Qwb_register: + case ARM::VST1d64Qwb_register: case ARM::VST2d8_UPD: case ARM::VST2d16_UPD: case ARM::VST2d32_UPD: @@ -2268,14 +2272,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, // Second input register switch (Inst.getOpcode()) { - case ARM::VST1d8Q: - case ARM::VST1d16Q: - case ARM::VST1d32Q: - case ARM::VST1d64Q: - case ARM::VST1d8Q_UPD: - case ARM::VST1d16Q_UPD: - case ARM::VST1d32Q_UPD: - case ARM::VST1d64Q_UPD: case ARM::VST2d8: case ARM::VST2d16: case ARM::VST2d32: @@ -2330,14 +2326,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, // Third input register switch (Inst.getOpcode()) { - case ARM::VST1d8Q: - case ARM::VST1d16Q: - case ARM::VST1d32Q: - case ARM::VST1d64Q: - case ARM::VST1d8Q_UPD: - case ARM::VST1d16Q_UPD: - case ARM::VST1d32Q_UPD: - case ARM::VST1d64Q_UPD: case ARM::VST2q8: case ARM::VST2q16: case ARM::VST2q32: @@ -2380,14 +2368,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, // Fourth input register switch (Inst.getOpcode()) { - case ARM::VST1d8Q: - case ARM::VST1d16Q: - case ARM::VST1d32Q: - case ARM::VST1d64Q: - case ARM::VST1d8Q_UPD: - case ARM::VST1d16Q_UPD: - case ARM::VST1d32Q_UPD: - case ARM::VST1d64Q_UPD: case ARM::VST2q8: case ARM::VST2q16: case ARM::VST2q32: |