diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-25 18:30:18 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-25 18:30:18 +0000 |
| commit | 99906830e82cf70dbcbed22237c7bd24f9d9ffdb (patch) | |
| tree | 7758dbb96d8aa0a3ff8ff781dd19c65d6ccf1a15 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | cf847bfa6f01645d023fbc959c207259ecb48391 (diff) | |
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 83a8f80060..0d945fdf59 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2539,8 +2539,8 @@ static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); } else if (Inst.getOpcode() == ARM::tADDspr) { unsigned Rm = fieldFromInstruction16(Insn, 3, 4); |