From 99906830e82cf70dbcbed22237c7bd24f9d9ffdb Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Thu, 25 Aug 2011 18:30:18 +0000 Subject: Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 83a8f80060..0d945fdf59 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2539,8 +2539,8 @@ static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); } else if (Inst.getOpcode() == ARM::tADDspr) { unsigned Rm = fieldFromInstruction16(Insn, 3, 4); -- cgit v1.2.3-18-g5258