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authorChad Rosier <mcrosier@apple.com>2012-08-31 17:24:10 +0000
committerChad Rosier <mcrosier@apple.com>2012-08-31 17:24:10 +0000
commit429af6fa4124d8b6dd310069e0a44dcacb35fc8a (patch)
treebe2a6000613e28b9158ef269600d32edd020c6a1 /lib/Target/ARM/AsmParser
parent5d04a560a875eef5cc7ae2bfadaf7d46ea8a60c5 (diff)
Add a comment to explain what's really going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163005 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser')
-rw-r--r--lib/Target/ARM/AsmParser/ARMAsmParser.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 1fde5a2e79..3ee3db5b02 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5347,6 +5347,12 @@ validateInstruction(MCInst &Inst,
case ARM::tMUL: {
// The second source operand must be the same register as the destination
// operand.
+ //
+ // In this case, we must directly check the parsed operands because the
+ // cvtThumbMultiply() function is written in such a way that it guarantees
+ // this first statement is always true for the new Inst. Essentially, the
+ // destination is unconditionally copied into the second source operand
+ // without checking to see if it matches what we actually parsed.
if (Operands.size() == 6 &&
(((ARMOperand*)Operands[3])->getReg() !=
((ARMOperand*)Operands[5])->getReg()) &&