diff options
| author | Jim Grosbach <grosbach@apple.com> | 2011-12-02 18:52:30 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-12-02 18:52:30 +0000 |
| commit | dad2f8e7fb2df5fb080a38fa4c33a01f19729f15 (patch) | |
| tree | 652f8343f120b677b0e591db9d274bcd5b049eb5 /lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | 30fe1ae20d02ac8e12cec9d767d855946546a030 (diff) | |
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 36 |
1 files changed, 32 insertions, 4 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 59dec0edfa..33b7eef67c 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -4754,8 +4754,22 @@ validateInstruction(MCInst &Inst, static unsigned getRealVLDNOpcode(unsigned Opc) { switch(Opc) { default: assert(0 && "unexpected opcode!"); - case ARM::VLD1LNd8asm: return ARM::VLD1LNd8; - case ARM::VLD1LNdf32asm: return ARM::VLD1LNd32; + case ARM::VLD1LNdAsm_8: return ARM::VLD1LNd8; + case ARM::VLD1LNdAsm_P8: return ARM::VLD1LNd8; + case ARM::VLD1LNdAsm_I8: return ARM::VLD1LNd8; + case ARM::VLD1LNdAsm_S8: return ARM::VLD1LNd8; + case ARM::VLD1LNdAsm_U8: return ARM::VLD1LNd8; + case ARM::VLD1LNdAsm_16: return ARM::VLD1LNd16; + case ARM::VLD1LNdAsm_P16: return ARM::VLD1LNd16; + case ARM::VLD1LNdAsm_I16: return ARM::VLD1LNd16; + case ARM::VLD1LNdAsm_S16: return ARM::VLD1LNd16; + case ARM::VLD1LNdAsm_U16: return ARM::VLD1LNd16; + case ARM::VLD1LNdAsm_32: return ARM::VLD1LNd32; + case ARM::VLD1LNdAsm_F: return ARM::VLD1LNd32; + case ARM::VLD1LNdAsm_F32: return ARM::VLD1LNd32; + case ARM::VLD1LNdAsm_I32: return ARM::VLD1LNd32; + case ARM::VLD1LNdAsm_S32: return ARM::VLD1LNd32; + case ARM::VLD1LNdAsm_U32: return ARM::VLD1LNd32; } } @@ -4764,8 +4778,22 @@ processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { switch (Inst.getOpcode()) { // Handle NEON VLD1 complex aliases. - case ARM::VLD1LNd8asm: - case ARM::VLD1LNdf32asm: { + case ARM::VLD1LNdAsm_8: + case ARM::VLD1LNdAsm_P8: + case ARM::VLD1LNdAsm_I8: + case ARM::VLD1LNdAsm_S8: + case ARM::VLD1LNdAsm_U8: + case ARM::VLD1LNdAsm_16: + case ARM::VLD1LNdAsm_P16: + case ARM::VLD1LNdAsm_I16: + case ARM::VLD1LNdAsm_S16: + case ARM::VLD1LNdAsm_U16: + case ARM::VLD1LNdAsm_32: + case ARM::VLD1LNdAsm_F: + case ARM::VLD1LNdAsm_F32: + case ARM::VLD1LNdAsm_I32: + case ARM::VLD1LNdAsm_S32: + case ARM::VLD1LNdAsm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. |