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| author | Daniel Dunbar <daniel@zuster.org> | 2011-01-10 15:26:21 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2011-01-10 15:26:21 +0000 |
| commit | 6a5c22ed89c8bb73034a70105340acf6539dc58b (patch) | |
| tree | a21c278925f41f2018eb489f4ee87c5969683e7a /lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | 083203dde8bd50e1be47ac6509ae52f43abcd12a (diff) | |
MC/ARM/AsmParser: Minor nitty fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123175 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index ed664e9554..d53ce93560 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -26,7 +26,7 @@ #include "llvm/ADT/Twine.h" using namespace llvm; -// The shift types for register controlled shifts in arm memory addressing +/// Shift types used for register controlled shifts in ARM memory addressing. enum ShiftType { Lsl, Lsr, @@ -134,7 +134,7 @@ class ARMOperand : public MCParsedAsmOperand { const MCExpr *Val; } Imm; - // This is for all forms of ARM address expressions + /// Combined record for all forms of ARM address expressions. struct { unsigned BaseRegNum; unsigned OffsetRegNum; // used when OffsetIsReg is true @@ -436,7 +436,7 @@ public: void ARMOperand::dump(raw_ostream &OS) const { switch (Kind) { case CondCode: - OS << ARMCondCodeToString(getCondCode()); + OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; break; case CCOut: OS << "<ccout " << getReg() << ">"; |