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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-08-17 17:09:40 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-08-17 17:09:40 +0000 |
| commit | f3a335cedff423438789c593d58be068b124dc1e (patch) | |
| tree | 0101525f562092cbaabf4a4ff64c971be4dfdb41 /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | d337295fb0f724d9da1e029260f68ef09b25e1fe (diff) | |
add a "load effective address"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29748 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index a9c30c40c7..c5eef11952 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -89,7 +89,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { MachineFunction &MF = *MBB.getParent(); assert (MI.getOpcode() == ARM::ldr || - MI.getOpcode() == ARM::str); + MI.getOpcode() == ARM::str || + MI.getOpcode() == ARM::lea_addri); unsigned FrameIdx = 2; unsigned OffIdx = 1; |