diff options
| author | Chris Lattner <sabre@nondot.org> | 2008-01-06 23:38:27 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-01-06 23:38:27 +0000 |
| commit | 834f1ce0312e3d00d836f9560cb63182c2c4570f (patch) | |
| tree | fa9d9d5b1ad73454fca5dd87fe5dd8b848b8bdc7 /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | 9e7aba2739fb3edb3ddcf04c5d36c7c1cccb0581 (diff) | |
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index ea775f74a1..316026234e 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -690,7 +690,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } unsigned Opcode = MI.getOpcode(); - const TargetInstrDescriptor &Desc = TII.get(Opcode); + const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); bool isSub = false; @@ -885,7 +885,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, assert(Offset && "This code isn't needed if offset already handled!"); if (isThumb) { - if (TII.isLoad(Opcode)) { + if (Desc.isSimpleLoad()) { // Use the destination register to materialize sp + offset. unsigned TmpReg = MI.getOperand(0).getReg(); bool UseRR = false; |