diff options
author | Evan Cheng <evan.cheng@apple.com> | 2007-05-29 18:42:18 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-05-29 18:42:18 +0000 |
commit | 62ccdbf0b3b75661bcdb20476609fece499c767f (patch) | |
tree | 0518d48460a3ea2ab72ea5c9c6991fad7235ce4b /lib/Target/ARM/ARMRegisterInfo.cpp | |
parent | f277ee4be7edabb759a7f78138b693d72d0c263f (diff) |
Add missing const qualifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
-rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 890542aa1d..41bafdcfff 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -1009,9 +1009,9 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (ScratchReg == 0) // No register is "free". Scavenge a register. ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); - MachineOperand *MO = MI.findFirstPredOperand(); - ARMCC::CondCodes Pred = MO ? - (ARMCC::CondCodes)MO->getImmedValue() : ARMCC::AL; + int PIdx = MI.findFirstPredOperandIdx(); + ARMCC::CondCodes Pred = (PIdx == -1) + ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue(); emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, Pred, isSub ? -Offset : Offset, TII); MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); |