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| author | Evan Cheng <evan.cheng@apple.com> | 2007-01-26 21:33:19 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-01-26 21:33:19 +0000 |
| commit | 3fdadfc9ab5fc1caf8c21b7b5cb8de1905f6dc60 (patch) | |
| tree | eb67e6cb677a6a60e5e6e7ace0f0444ec2a97a39 /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | 44c3b9fdd416c79f4b67cde1aecfced5921efd81 (diff) | |
Represent tADDspi and tSUBspi as two-address instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33551 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 68eb616d7f..912d17adc1 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -378,7 +378,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, Bytes -= ThisVal; // Build the new tADD / tSUB. if (isTwoAddr) - BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addImm(ThisVal); + BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); else { BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal); BaseReg = DestReg; |