diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-09-13 12:09:43 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-09-13 12:09:43 +0000 |
| commit | 3ad5e5cf998841681e9d11e08eb82a94ddffd1f8 (patch) | |
| tree | 05fd5e609b136c6c04f3b3c5ff8e65bbb955dfae /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | c970f062e0a66d97a06eca213486a16fae1b37a4 (diff) | |
add shifts to addressing mode 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index d5f6caaa4c..1b0f3fd8e5 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -48,7 +48,8 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const { assert (RC == ARM::IntRegsRegisterClass); - BuildMI(MBB, I, ARM::MOV, 1, DestReg).addReg(SrcReg); + BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0) + .addImm(ARMShift::LSL); } MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI, @@ -114,7 +115,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { // Insert a set of r12 with the full address // r12 = r13 + offset MachineBasicBlock *MBB2 = MI.getParent(); - BuildMI(*MBB2, II, ARM::ADD, 2, ARM::R12).addReg(ARM::R13).addImm(Offset); + BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(ARM::R13).addImm(Offset) + .addImm(0).addImm(ARMShift::LSL); // Replace the FrameIndex with r12 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false); @@ -140,7 +142,8 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { MFI->setStackSize(NumBytes); //sub sp, sp, #NumBytes - BuildMI(MBB, MBBI, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes); + BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes) + .addImm(0).addImm(ARMShift::LSL); } void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, @@ -153,7 +156,8 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, int NumBytes = (int) MFI->getStackSize(); //add sp, sp, #NumBytes - BuildMI(MBB, MBBI, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes); + BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes) + .addImm(0).addImm(ARMShift::LSL); } unsigned ARMRegisterInfo::getRARegister() const { |