diff options
| author | Chris Lattner <sabre@nondot.org> | 2008-01-06 08:36:04 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-01-06 08:36:04 +0000 |
| commit | 2e48a70b35635165703838fc8d3796b664207aa1 (patch) | |
| tree | a6a26cefc34c30d6506057ef070a82b9768fe1fe /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | 920595a960fbebbf614dd159d54fc2e7ea279c22 (diff) | |
rename isStore -> mayStore to more accurately reflect what it captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index b940052de9..ea775f74a1 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -905,7 +905,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); else // tLDR has an extra register operand. MI.addOperand(MachineOperand::CreateReg(0, false)); - } else if (TII.isStore(Opcode)) { + } else if (TII.mayStore(Opcode)) { // FIXME! This is horrific!!! We need register scavenging. // Our temporary workaround has marked r3 unavailable. Of course, r3 is // also a ABI register so it's possible that is is the register that is |