diff options
| author | Bill Wendling <isanbard@gmail.com> | 2010-10-14 02:33:26 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-10-14 02:33:26 +0000 |
| commit | bbbdcd453d22258cb4dd217eddf016668fcebf84 (patch) | |
| tree | ea56c8202a8f47594ca62fb4d655f01927163a42 /lib/Target/ARM/ARMMCCodeEmitter.cpp | |
| parent | 946a2740a54fe2cd57509999384239101bf5b9df (diff) | |
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMMCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 5b20676961..cafd3f235c 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -138,10 +138,13 @@ EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, /// operand requires relocation, record the relocation and return zero. unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO) const { - if (MO.isReg()) + if (MO.isReg()) { return getARMRegisterNumbering(MO.getReg()); - else if (MO.isImm()) { + } else if (MO.isImm()) { return static_cast<unsigned>(MO.getImm()); + } else if (MO.isFPImm()) { + return static_cast<unsigned>(APFloat(MO.getFPImm()) + .bitcastToAPInt().getHiBits(32).getLimitedValue()); } else { #ifndef NDEBUG errs() << MO; @@ -151,7 +154,6 @@ unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI, return 0; } - unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI, unsigned OpIdx) const { // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg |