diff options
| author | Owen Anderson <resistor@mac.com> | 2010-10-21 20:49:13 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2010-10-21 20:49:13 +0000 |
| commit | 90d4cf931477b497553a9f2d0ed53377dd5dd88c (patch) | |
| tree | a0cd3604aa8912fc504199224687d6412d8faad8 /lib/Target/ARM/ARMMCCodeEmitter.cpp | |
| parent | 4bcb949e18d930765b4f0aabf93cc484dce9d159 (diff) | |
Move the encoding logic for Q registers into getMachineOpValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117060 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMMCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 6132d6df7f..ea7789c073 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -143,7 +143,18 @@ EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO) const { if (MO.isReg()) { - return getARMRegisterNumbering(MO.getReg()); + unsigned regno = getARMRegisterNumbering(MO.getReg()); + + // Q registers are encodes as 2x their register number. + switch (MO.getReg()) { + case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: + case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: + case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: + case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: + return 2 * regno; + default: + return regno; + } } else if (MO.isImm()) { return static_cast<unsigned>(MO.getImm()); } else if (MO.isFPImm()) { |