diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-10-27 00:38:16 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-10-27 00:38:16 +0000 |
| commit | f85dd04bfaba4b7d57833d576127439628cb2931 (patch) | |
| tree | aeecd0eb2d10808aca8c9a6e33b91f3919084513 /lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | a06038369b830bb83742b6b39775f39dd9e69ae2 (diff) | |
One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 85a0981ec6..3715ec002c 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -860,7 +860,9 @@ static void InsertLDR_STR(MachineBasicBlock &MBB, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) { int Offset = OffImm; - if (!isT2) { + // FIXME: This fancy offset encoding stuff goes away when we're done + // removing addrmode2. + if (!isT2 && !isDef) { if (OffImm < 0) Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift); else @@ -871,8 +873,6 @@ static void InsertLDR_STR(MachineBasicBlock &MBB, TII->get(NewOpc)) .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); - if (!isT2) - MIB.addReg(OffReg, getKillRegState(OffKill)|getUndefRegState(OffUndef)); MIB.addImm(Offset).addImm(Pred).addReg(PredReg); } else { MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), |