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| author | Evan Cheng <evan.cheng@apple.com> | 2009-08-04 21:12:13 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-08-04 21:12:13 +0000 |
| commit | 9e7a312391cb955bfc148d15a69adcaf7cc3ae50 (patch) | |
| tree | af670a42b6bf6334e9f7a975c69dd19bf74b4181 /lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 275bb1bd1284b932bd7a2352f04e462ad7c33cd2 (diff) | |
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index c6afbe9336..a81b790f9d 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -615,12 +615,15 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB, return false; bool isDPR = NewOpc == ARM::FLDMD || NewOpc == ARM::FSTMD; - unsigned Offset = isAM5 - ? ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) ? ARM_AM::db : ARM_AM::ia, - true, isDPR ? 2 : 1) - : (isAM2 - ? ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift) - : Bytes); + unsigned Offset = 0; + if (isAM5) + Offset = ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) + ? ARM_AM::db + : ARM_AM::ia, true, (isDPR ? 2 : 1)); + else if (isAM2) + Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); + else + Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes; if (isLd) { if (isAM5) // FLDMS, FLDMD |