The machine instruction no longer encodes the submode as a separate operand. We

should get the submode from the load/store multiple instruction's opcode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 2 deletions

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 10dfd16fe9..eb85dafbc6 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -206,7 +206,10 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
   return 0;
 }
 
-static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
+namespace llvm {
+  namespace ARM_AM {
+
+AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
   switch (Opcode) {
   default: llvm_unreachable("Unhandled opcode!");
   case ARM::LDMIA:
@@ -241,6 +244,9 @@ static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
   return ARM_AM::bad_am_submode;
 }
 
+  } // end namespace ARM_AM
+} // end namespace llvm
+
 static bool isT2i32Load(unsigned Opc) {
   return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
 }
@@ -670,7 +676,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
       return false;
 
   bool DoMerge = false;
-  ARM_AM::AMSubMode Mode = getLoadStoreMultipleSubMode(Opcode);
+  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(Opcode);
 
   // Try merging with the previous instruction.
   MachineBasicBlock::iterator BeginMBBI = MBB.begin();