Fix ARM condition code subsumission check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37517 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 3 insertions, 3 deletions

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 867ce063b1..0d0b813914 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -471,13 +471,13 @@ ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
   case ARMCC::AL:
     return true;
   case ARMCC::HS:
-    return CC2 == ARMCC::HI || CC2 == ARMCC::EQ;
+    return CC2 == ARMCC::HI;
   case ARMCC::LS:
     return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
   case ARMCC::GE:
-    return CC2 == ARMCC::GT || CC2 == ARMCC::EQ;
+    return CC2 == ARMCC::GT;
   case ARMCC::LE:
-    return CC2 == ARMCC::LT || CC2 == ARMCC::EQ;
+    return CC2 == ARMCC::LT;
   }
 }