Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the

vabd intrinsic and add and/or zext operations.  In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests.  Auto-upgrade the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 17 deletions

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 0a41d6d957..ce4a2c9068 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -4293,28 +4293,11 @@ SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
 /// operands.
 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
                                          TargetLowering::DAGCombinerInfo &DCI) {
-  SelectionDAG &DAG = DCI.DAG;
-
   // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
   if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
     SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
     if (Result.getNode()) return Result;
   }
-
-  // fold (add (arm_neon_vabd a, b) c) -> (arm_neon_vaba c, a, b)
-  EVT VT = N->getValueType(0);
-  if (N0.getOpcode() == ISD::INTRINSIC_WO_CHAIN && VT.isInteger()) {
-    unsigned IntNo = cast<ConstantSDNode>(N0.getOperand(0))->getZExtValue();
-    if (IntNo == Intrinsic::arm_neon_vabds)
-      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), VT,
-                         DAG.getConstant(Intrinsic::arm_neon_vabas, MVT::i32),
-                         N1, N0.getOperand(1), N0.getOperand(2));
-    if (IntNo == Intrinsic::arm_neon_vabdu)
-      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), VT,
-                         DAG.getConstant(Intrinsic::arm_neon_vabau, MVT::i32),
-                         N1, N0.getOperand(1), N0.getOperand(2));
-  }
-
   return SDValue();
 }