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| author | Jim Grosbach <grosbach@apple.com> | 2013-03-02 20:16:19 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2013-03-02 20:16:19 +0000 |
| commit | 65da9f1ce14800c137fcd8c32f3ad12c9bebd9bf (patch) | |
| tree | 2c6dcf238c6df0d804cfd9c8b19fd99b66334a60 /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 7ccf46395e02ecaff6e6cab6ad258c69893efd55 (diff) | |
Clean up code format a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176412 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 0f55e3a17c..5d24e92f23 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -4468,12 +4468,10 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT), Value, DAG.getConstant(index, MVT::i32)), DAG.getConstant(index, MVT::i32)); - } else { + } else N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, Value->getOperand(0), Value->getOperand(1)); - } - } - else + } else N = DAG.getNode(ARMISD::VDUP, dl, VT, Value); if (!usesOnlyOneValue) { |