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| author | Evan Cheng <evan.cheng@apple.com> | 2008-10-14 21:26:46 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-10-14 21:26:46 +0000 |
| commit | 0329466b6b4927f4e6f5d144891fef06a027fec5 (patch) | |
| tree | 76dc7bdfd70c4c7b0c0d983f1787d236629c4913 /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 2642196a6570e95e1491ee0120f67baa5c3ea351 (diff) | |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index e70bb0bd96..14c4526d1a 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -131,10 +131,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) computeRegisterProperties(); // ARM does not have f32 extending load. - setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); // ARM does not have i1 sign extending load. - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); // ARM supports all 4 flavors of integer indexed load / store. for (unsigned im = (unsigned)ISD::PRE_INC; |