diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-10-27 23:12:14 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-10-27 23:12:14 +0000 |
| commit | 7e3383c007f53b3a00675af225e428cb66ddf404 (patch) | |
| tree | a506d6a7aa8416c28debbaa7905253d71d2dd4d5 /lib/Target/ARM/ARMAsmPrinter.cpp | |
| parent | 0bccec368a55e80a2911dcb448cdffabf6bcea98 (diff) | |
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMAsmPrinter.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 79b35ad4b9..8e21592199 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -870,8 +870,8 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { switch (MI->getOpcode()) { default: llvm_unreachable("Unexpected opcode!"); - case ARM::PICSTR: Opcode = ARM::STR; break; - case ARM::PICSTRB: Opcode = ARM::STRB; break; + case ARM::PICSTR: Opcode = ARM::STRrs; break; + case ARM::PICSTRB: Opcode = ARM::STRBrs; break; case ARM::PICSTRH: Opcode = ARM::STRH; break; case ARM::PICLDR: Opcode = ARM::LDRrs; break; case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; @@ -1161,10 +1161,9 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } { MCInst TmpInst; - TmpInst.setOpcode(ARM::STR); + TmpInst.setOpcode(ARM::STRi12); TmpInst.addOperand(MCOperand::CreateReg(ValReg)); TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateReg(0)); TmpInst.addOperand(MCOperand::CreateImm(4)); // Predicate. TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); |