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authorAndrew Trick <atrick@apple.com>2012-09-18 03:18:56 +0000
committerAndrew Trick <atrick@apple.com>2012-09-18 03:18:56 +0000
commite127dfd0b175b5a336e61fecaad7fc2aec65d95c (patch)
tree4757561e728399b5f74422859e930881a8e9fc5e /lib/MC
parent0cb0a3533788c6c622518cb030048012eb69af15 (diff)
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/MC')
-rw-r--r--lib/MC/MCSubtargetInfo.cpp10
1 files changed, 9 insertions, 1 deletions
diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp
index 47735a492d..34b7eeabbc 100644
--- a/lib/MC/MCSubtargetInfo.cpp
+++ b/lib/MC/MCSubtargetInfo.cpp
@@ -24,6 +24,9 @@ MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *ProcSched,
+ const MCWriteProcResEntry *WPR,
+ const MCWriteLatencyEntry *WL,
+ const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC,
const unsigned *FP,
@@ -32,6 +35,10 @@ MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
ProcFeatures = PF;
ProcDesc = PD;
ProcSchedModels = ProcSched;
+ WriteProcResTable = WPR;
+ WriteLatencyTable = WL;
+ ReadAdvanceTable = RA;
+
Stages = IS;
OperandCycles = OC;
ForwardingPaths = FP;
@@ -41,8 +48,9 @@ MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
SubtargetFeatures Features(FS);
FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
ProcFeatures, NumFeatures);
-}
+ CPUSchedModel = getSchedModelForCPU(CPU);
+}
/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
/// feature string) and recompute feature bits.