Qualify several calls to functions in the MVT namespace, for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37230 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 25 insertions, 23 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4abb68b2a7..294f46ade7 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2722,7 +2722,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     case TargetLowering::Promote: {
       MVT::ValueType OVT = Tmp1.getValueType();
       MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
-      unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
+      unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
 
       Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
       Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
@@ -2760,16 +2760,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       case ISD::CTTZ:
         //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
         Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
-                            DAG.getConstant(getSizeInBits(NVT), NVT),
+                            DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
                             ISD::SETEQ);
         Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
-                           DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
+                           DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
         break;
       case ISD::CTLZ:
         // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
         Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
-                             DAG.getConstant(getSizeInBits(NVT) -
-                                             getSizeInBits(OVT), NVT));
+                             DAG.getConstant(MVT::getSizeInBits(NVT) -
+                                             MVT::getSizeInBits(OVT), NVT));
         break;
       }
       break;
@@ -3527,7 +3527,8 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
     Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
     Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
-                         DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
+                         DAG.getConstant(MVT::getSizeInBits(NVT) -
+                                         MVT::getSizeInBits(VT),
                                          TLI.getShiftAmountTy()));
     break;
   case ISD::CTPOP:
@@ -3544,15 +3545,16 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     case ISD::CTTZ:
       // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
       Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
-                          DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
+                          DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
+                          ISD::SETEQ);
       Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
-                           DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
+                           DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
       break;
     case ISD::CTLZ:
       //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
       Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
-                           DAG.getConstant(getSizeInBits(NVT) -
-                                           getSizeInBits(VT), NVT));
+                           DAG.getConstant(MVT::getSizeInBits(NVT) -
+                                           MVT::getSizeInBits(VT), NVT));
       break;
     }
     break;
@@ -4639,7 +4641,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
     };
     MVT::ValueType VT = Op.getValueType();
     MVT::ValueType ShVT = TLI.getShiftAmountTy();
-    unsigned len = getSizeInBits(VT);
+    unsigned len = MVT::getSizeInBits(VT);
     for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
       //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
       SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
@@ -4662,7 +4664,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
     // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
     MVT::ValueType VT = Op.getValueType();
     MVT::ValueType ShVT = TLI.getShiftAmountTy();
-    unsigned len = getSizeInBits(VT);
+    unsigned len = MVT::getSizeInBits(VT);
     for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
       SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
       Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
@@ -4684,7 +4686,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
     if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
         TLI.isOperationLegal(ISD::CTLZ, VT))
       return DAG.getNode(ISD::SUB, VT,
-                         DAG.getConstant(getSizeInBits(VT), VT),
+                         DAG.getConstant(MVT::getSizeInBits(VT), VT),
                          DAG.getNode(ISD::CTLZ, VT, Tmp3));
     return DAG.getNode(ISD::CTPOP, VT, Tmp3);
   }
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 19f10ebf2a..7fd1938e7a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -310,14 +310,14 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
     const VectorType *PTy = cast<VectorType>(V->getType());
     unsigned NumElts = PTy->getNumElements();
     MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
-    MVT::ValueType VecTy = getVectorType(EltTy, NumElts);
+    MVT::ValueType VecTy = MVT::getVectorType(EltTy, NumElts);
     
     // Divide the input until we get to a supported size.  This will always
     // end with a scalar if the target doesn't support vectors.
     while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
       NumElts >>= 1;
       NumVectorRegs <<= 1;
-      VecTy = getVectorType(EltTy, NumElts);
+      VecTy = MVT::getVectorType(EltTy, NumElts);
     }
 
     // Check that VecTy isn't a 1-element vector.
@@ -1689,7 +1689,7 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
                                                     CaseRecVector& WorkList,
                                                     Value* SV,
                                                     MachineBasicBlock* Default){
-  unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
+  unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
 
   Case& FrontCase = *CR.Range.first;
   Case& BackCase  = *(CR.Range.second-1);
@@ -4187,7 +4187,7 @@ static SDOperand getMemsetStringVal(MVT::ValueType VT,
                                     SelectionDAG &DAG, TargetLowering &TLI,
                                     std::string &Str, unsigned Offset) {
   uint64_t Val = 0;
-  unsigned MSB = getSizeInBits(VT) / 8;
+  unsigned MSB = MVT::getSizeInBits(VT) / 8;
   if (TLI.isLittleEndian())
     Offset = Offset + MSB - 1;
   for (unsigned i = 0; i != MSB; ++i) {
@@ -4241,7 +4241,7 @@ static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
 
   unsigned NumMemOps = 0;
   while (Size != 0) {
-    unsigned VTSize = getSizeInBits(VT) / 8;
+    unsigned VTSize = MVT::getSizeInBits(VT) / 8;
     while (VTSize > Size) {
       VT = (MVT::ValueType)((unsigned)VT - 1);
       VTSize >>= 1;
@@ -4280,7 +4280,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
         unsigned Offset = 0;
         for (unsigned i = 0; i < NumMemOps; i++) {
           MVT::ValueType VT = MemOps[i];
-          unsigned VTSize = getSizeInBits(VT) / 8;
+          unsigned VTSize = MVT::getSizeInBits(VT) / 8;
           SDOperand Value = getMemsetValue(Op2, VT, DAG);
           SDOperand Store = DAG.getStore(getRoot(), Value,
                                     getMemBasePlusOffset(Op1, Offset, DAG, TLI),
@@ -4321,7 +4321,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
 
         for (unsigned i = 0; i < NumMemOps; i++) {
           MVT::ValueType VT = MemOps[i];
-          unsigned VTSize = getSizeInBits(VT) / 8;
+          unsigned VTSize = MVT::getSizeInBits(VT) / 8;
           SDOperand Value, Chain, Store;
 
           if (CopyFromStr) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 5ff8d8769a..dbe101f9f4 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -145,7 +145,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
     else
       Op += "<null:" + itostr(M->getOffset()) + ">";
   } else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) {
-    Op = Op + " VT=" + getValueTypeString(N->getVT());
+    Op = Op + " VT=" + MVT::getValueTypeString(N->getVT());
   } else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) {
     Op = Op + "\"" + N->getValue() + "\"";
   } else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Node)) {
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a0125d395d..a2cd12801d 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -299,12 +299,12 @@ unsigned TargetLowering::getVectorTypeBreakdown(const VectorType *PTy,
   
   // Divide the input until we get to a supported size.  This will always
   // end with a scalar if the target doesn't support vectors.
-  while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
+  while (NumElts > 1 && !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
     NumElts >>= 1;
     NumVectorRegs <<= 1;
   }
   
-  MVT::ValueType VT = getVectorType(EltTy, NumElts);
+  MVT::ValueType VT = MVT::getVectorType(EltTy, NumElts);
   if (!isTypeLegal(VT))
     VT = EltTy;
   PTyElementVT = VT;