- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 5 insertions, 24 deletions

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 3d2565dd18..e01f0ab1ce 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -527,10 +527,10 @@ void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
   MachineInstr *DefMI = Def->getInstr();
   int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
   if (DefIdx != -1) {
-    unsigned DefClass = DefMI->getDesc().getSchedClass();
-    MachineInstr *UseMI = Use->getInstr();
-    unsigned UseClass = UseMI->getDesc().getSchedClass();
+    const TargetInstrDesc &DefTID = DefMI->getDesc();
+    unsigned DefClass = DefTID.getSchedClass();
 
+    MachineInstr *UseMI = Use->getInstr();
     // For all uses of the register, calculate the maxmimum latency
     int Latency = -1;
     for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
@@ -541,8 +541,7 @@ void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
       if (MOReg != Reg)
         continue;
 
-      int UseCycle = InstrItins->getOperandLatency(DefClass, DefIdx,
-                                                   UseClass, i);
+      int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx, UseMI, i);
       Latency = std::max(Latency, UseCycle);
 
       // If we found a latency, then replace the existing dependence latency.
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 23ff9c5807..0ffb4da0f3 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -450,29 +450,11 @@ void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
   if (ForceUnitLatencies())
     return;
 
-  if (!InstrItins || InstrItins->isEmpty())
-    return;
-  
   if (dep.getKind() != SDep::Data)
     return;
 
   unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
-  if (!Def->isMachineOpcode())
-    return;
-
-  const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
-  if (DefIdx >= II.getNumDefs())
-    return;
-
-  int Latency = 0;
-  if (!Use->isMachineOpcode()) {
-    Latency = InstrItins->getOperandCycle(II.getSchedClass(), DefIdx);
-  } else {
-    unsigned DefClass = II.getSchedClass();
-    unsigned UseClass = TII->get(Use->getMachineOpcode()).getSchedClass();
-    Latency = InstrItins->getOperandLatency(DefClass, DefIdx, UseClass, OpIdx);
-  }
-
+  int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
   if (Latency >= 0)
     dep.setLatency(Latency);
 }