Make dense maps keyed on physical registers smallerusing

MRegisterInfo::getNumRegs() instead of
MRegisterInfo::FirstVirtualRegister.

Also use MRegisterInfo::is{Physical,Virtual}Register where
appropriate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11477 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 6 insertions, 7 deletions

diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 420cb4443e..0554bae87b 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -187,10 +187,9 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
   // physical register.  This is a purely local property, because all physical
   // register references as presumed dead across basic blocks.
   //
-  MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister];
-  bool          PhysRegUsedA[MRegisterInfo::FirstVirtualRegister];
-  std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister,
-	    (MachineInstr*)0);
+  MachineInstr *PhysRegInfoA[RegInfo->getNumRegs()];
+  bool          PhysRegUsedA[RegInfo->getNumRegs()];
+  std::fill(PhysRegInfoA, PhysRegInfoA+RegInfo->getNumRegs(), (MachineInstr*)0);
   PhysRegInfo = PhysRegInfoA;
   PhysRegUsed = PhysRegUsedA;
 
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 30e7eb6958..4082019dfc 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -98,7 +98,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
     return;
 
   // This bitset contains an entry for each physical register for the target...
-  std::vector<bool> ModifiedRegs(MRegisterInfo::FirstVirtualRegister);
+  std::vector<bool> ModifiedRegs(RegInfo->getNumRegs());
   unsigned MaxCallFrameSize = 0;
   bool HasCalls = false;
 
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index f9abd68e14..1ca7f0c440 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -53,7 +53,7 @@ namespace {
     std::vector<unsigned> Virt2PhysRegMap;
 
     unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
-      assert(VirtReg >= MRegisterInfo::FirstVirtualRegister &&"Illegal VREG #");
+      assert(MRegisterInfo::isVirtualRegister(VirtReg) &&"Illegal VREG #");
       assert(VirtReg-MRegisterInfo::FirstVirtualRegister <Virt2PhysRegMap.size()
              && "VirtReg not in map!");
       return Virt2PhysRegMap[VirtReg-MRegisterInfo::FirstVirtualRegister];
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index e313004ff4..a81edda858 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -154,7 +154,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     // Made to combat the incorrect allocation of r2 = add r1, r1
     std::map<unsigned, unsigned> Virt2PhysRegMap;
 
-    RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
+    RegsUsed.resize(RegInfo->getNumRegs());
     
     // a preliminary pass that will invalidate any registers that
     // are used by the instruction (including implicit uses)