Wrap MVT::ValueType in a struct to get type safety

and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8

16 files changed, 1255 insertions, 1279 deletions

diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
index 667870d452..5dcf4ac92d 100644
--- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
+++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
@@ -32,8 +32,8 @@ CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm,
 // HandleByVal - Allocate a stack slot large enough to pass an argument by
 // value. The size and alignment information of the argument is encoded in its
 // parameter attribute.
-void CCState::HandleByVal(unsigned ValNo, MVT::ValueType ValVT,
-                          MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
+void CCState::HandleByVal(unsigned ValNo, MVT ValVT,
+                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                           int MinSize, int MinAlign,
                           ISD::ArgFlagsTy ArgFlags) {
   unsigned Align = ArgFlags.getByValAlign();
@@ -62,12 +62,12 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
   unsigned NumArgs = TheArgs->getNumValues()-1;
   
   for (unsigned i = 0; i != NumArgs; ++i) {
-    MVT::ValueType ArgVT = TheArgs->getValueType(i);
+    MVT ArgVT = TheArgs->getValueType(i);
     ISD::ArgFlagsTy ArgFlags =
       cast<ARG_FLAGSSDNode>(TheArgs->getOperand(3+i))->getArgFlags();
     if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
       cerr << "Formal argument #" << i << " has unhandled type "
-           << MVT::getValueTypeString(ArgVT) << "\n";
+           << ArgVT.getMVTString() << "\n";
       abort();
     }
   }
@@ -78,12 +78,12 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
 void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
   // Determine which register each value should be copied into.
   for (unsigned i = 0, e = TheRet->getNumOperands() / 2; i != e; ++i) {
-    MVT::ValueType VT = TheRet->getOperand(i*2+1).getValueType();
+    MVT VT = TheRet->getOperand(i*2+1).getValueType();
     ISD::ArgFlagsTy ArgFlags =
       cast<ARG_FLAGSSDNode>(TheRet->getOperand(i*2+2))->getArgFlags();
     if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){
       cerr << "Return operand #" << i << " has unhandled type "
-           << MVT::getValueTypeString(VT) << "\n";
+           << VT.getMVTString() << "\n";
       abort();
     }
   }
@@ -95,12 +95,12 @@ void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
 void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) {
   unsigned NumOps = (TheCall->getNumOperands() - 5) / 2;
   for (unsigned i = 0; i != NumOps; ++i) {
-    MVT::ValueType ArgVT = TheCall->getOperand(5+2*i).getValueType();
+    MVT ArgVT = TheCall->getOperand(5+2*i).getValueType();
     ISD::ArgFlagsTy ArgFlags =
       cast<ARG_FLAGSSDNode>(TheCall->getOperand(5+2*i+1))->getArgFlags();
     if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
       cerr << "Call operand #" << i << " has unhandled type "
-           << MVT::getValueTypeString(ArgVT) << "\n";
+           << ArgVT.getMVTString() << "\n";
       abort();
     }
   }
@@ -110,10 +110,10 @@ void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) {
 /// incorporating info about the passed values into this state.
 void CCState::AnalyzeCallResult(SDNode *TheCall, CCAssignFn Fn) {
   for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
-    MVT::ValueType VT = TheCall->getValueType(i);
+    MVT VT = TheCall->getValueType(i);
     if (Fn(i, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
       cerr << "Call result #" << i << " has unhandled type "
-           << MVT::getValueTypeString(VT) << "\n";
+           << VT.getMVTString() << "\n";
       abort();
     }
   }
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 31cbdb9c78..d957bf9353 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -215,12 +215,12 @@ namespace {
     SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 
                                SDOperand N3, ISD::CondCode CC, 
                                bool NotExtCompare = false);
-    SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
+    SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
                             ISD::CondCode Cond, bool foldBooleans = true);
     SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 
                                          unsigned HiOp);
-    SDOperand CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT);
-    SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
+    SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT);
+    SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
     SDOperand BuildSDIV(SDNode *N);
     SDOperand BuildUDIV(SDNode *N);
     SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
@@ -482,7 +482,7 @@ static bool isOneUseSetCC(SDOperand N) {
 }
 
 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
   // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
   // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
   if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
@@ -887,7 +887,7 @@ SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) {
 
 static
 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
   SDOperand N00 = N0.getOperand(0);
   SDOperand N01 = N0.getOperand(1);
   ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
@@ -904,7 +904,7 @@ SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
 static
 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
                               SelectionDAG &DAG) {
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   unsigned Opc = N->getOpcode();
   bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
   SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
@@ -930,8 +930,8 @@ SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
            cast<ConstantSDNode>(RHS)->isNullValue()) {
     std::swap(LHS, RHS);
     SDOperand Op0 = Slct.getOperand(0);
-    bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType()
-                                : Op0.getOperand(0).getValueType());
+    bool isInt = (isSlctCC ? Op0.getValueType() :
+                  Op0.getOperand(0).getValueType()).isInteger();
     CC = ISD::getSetCCInverse(CC, isInt);
     DoXform = true;
     InvCC = true;
@@ -956,10 +956,10 @@ SDOperand DAGCombiner::visitADD(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
 
   // fold vector ops
-  if (MVT::isVector(VT)) {
+  if (VT.isVector()) {
     SDOperand FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.Val) return FoldedVOp;
   }
@@ -1001,14 +1001,14 @@ SDOperand DAGCombiner::visitADD(SDNode *N) {
   if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
     return N1.getOperand(0);
 
-  if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
+  if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0)))
     return SDOperand(N, 0);
   
   // fold (a+b) -> (a|b) iff a and b share no bits.
-  if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
+  if (VT.isInteger() && !VT.isVector()) {
     APInt LHSZero, LHSOne;
     APInt RHSZero, RHSOne;
-    APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
+    APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
     DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
     if (LHSZero.getBoolValue()) {
       DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
@@ -1049,7 +1049,7 @@ SDOperand DAGCombiner::visitADDC(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
   
   // If the flag result is dead, turn this into an ADD.
   if (N->hasNUsesOfValue(0, 1))
@@ -1069,7 +1069,7 @@ SDOperand DAGCombiner::visitADDC(SDNode *N) {
   // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
   APInt LHSZero, LHSOne;
   APInt RHSZero, RHSOne;
-  APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
+  APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
   DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
   if (LHSZero.getBoolValue()) {
     DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
@@ -1091,7 +1091,7 @@ SDOperand DAGCombiner::visitADDE(SDNode *N) {
   SDOperand CarryIn = N->getOperand(2);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  //MVT::ValueType VT = N0.getValueType();
+  //MVT VT = N0.getValueType();
   
   // canonicalize constant to RHS
   if (N0C && !N1C) {
@@ -1115,10 +1115,10 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
   
   // fold vector ops
-  if (MVT::isVector(VT)) {
+  if (VT.isVector()) {
     SDOperand FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.Val) return FoldedVOp;
   }
@@ -1158,10 +1158,10 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
   
   // fold vector ops
-  if (MVT::isVector(VT)) {
+  if (VT.isVector()) {
     SDOperand FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.Val) return FoldedVOp;
   }
@@ -1242,10 +1242,10 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
 
   // fold vector ops
-  if (MVT::isVector(VT)) {
+  if (VT.isVector()) {
     SDOperand FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.Val) return FoldedVOp;
   }
@@ -1261,7 +1261,7 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
     return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
   // If we know the sign bits of both operands are zero, strength reduce to a
   // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
-  if (!MVT::isVector(VT)) {
+  if (!VT.isVector()) {
     if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
       return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
   }
@@ -1278,12 +1278,12 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
     unsigned lg2 = Log2_64(abs2);
     // Splat the sign bit into the register
     SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
-                                DAG.getConstant(MVT::getSizeInBits(VT)-1,
+                                DAG.getConstant(VT.getSizeInBits()-1,
                                                 TLI.getShiftAmountTy()));
     AddToWorkList(SGN.Val);
     // Add (N0 < 0) ? abs2 - 1 : 0;
     SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
-                                DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
+                                DAG.getConstant(VT.getSizeInBits()-lg2,
                                                 TLI.getShiftAmountTy()));
     SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
     AddToWorkList(SRL.Val);
@@ -1320,10 +1320,10 @@ SDOperand DAGCombiner::visitUDIV(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   
   // fold vector ops
-  if (MVT::isVector(VT)) {
+  if (VT.isVector()) {
     SDOperand FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.Val) return FoldedVOp;
   }
@@ -1340,7 +1340,7 @@ SDOperand DAGCombiner::visitUDIV(SDNode *N) {
   if (N1.getOpcode() == ISD::SHL) {
     if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
       if (SHC->getAPIntValue().isPowerOf2()) {
-        MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
+        MVT ADDVT = N1.getOperand(1).getValueType();
         SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
                                     DAG.getConstant(SHC->getAPIntValue()
                                                                     .logBase2(),
@@ -1371,14 +1371,14 @@ SDOperand DAGCombiner::visitSREM(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   
   // fold (srem c1, c2) -> c1%c2
   if (N0C && N1C && !N1C->isNullValue())
     return DAG.getNode(ISD::SREM, VT, N0, N1);
   // If we know the sign bits of both operands are zero, strength reduce to a
   // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
-  if (!MVT::isVector(VT)) {
+  if (!VT.isVector()) {
     if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
       return DAG.getNode(ISD::UREM, VT, N0, N1);
   }
@@ -1412,7 +1412,7 @@ SDOperand DAGCombiner::visitUREM(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   
   // fold (urem c1, c2) -> c1%c2
   if (N0C && N1C && !N1C->isNullValue())
@@ -1427,7 +1427,7 @@ SDOperand DAGCombiner::visitUREM(SDNode *N) {
       if (SHC->getAPIntValue().isPowerOf2()) {
         SDOperand Add =
           DAG.getNode(ISD::ADD, VT, N1,
-                 DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)),
+                 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
                                  VT));
         AddToWorkList(Add.Val);
         return DAG.getNode(ISD::AND, VT, N0, Add);
@@ -1462,7 +1462,7 @@ SDOperand DAGCombiner::visitMULHS(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   
   // fold (mulhs x, 0) -> 0
   if (N1C && N1C->isNullValue())
@@ -1470,7 +1470,7 @@ SDOperand DAGCombiner::visitMULHS(SDNode *N) {
   // fold (mulhs x, 1) -> (sra x, size(x)-1)
   if (N1C && N1C->getAPIntValue() == 1)
     return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 
-                       DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
+                       DAG.getConstant(N0.getValueType().getSizeInBits()-1,
                                        TLI.getShiftAmountTy()));
   // fold (mulhs x, undef) -> 0
   if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
@@ -1483,7 +1483,7 @@ SDOperand DAGCombiner::visitMULHU(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   
   // fold (mulhu x, 0) -> 0
   if (N1C && N1C->isNullValue())
@@ -1583,7 +1583,7 @@ SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
 /// two operands of the same opcode, try to simplify it.
 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
   SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
   assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
   
   // For each of OP in AND/OR/XOR:
@@ -1624,11 +1624,11 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
   SDOperand LL, LR, RL, RR, CC0, CC1;
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N1.getValueType();
-  unsigned BitWidth = MVT::getSizeInBits(VT);
+  MVT VT = N1.getValueType();
+  unsigned BitWidth = VT.getSizeInBits();
   
   // fold vector ops
-  if (MVT::isVector(VT)) {
+  if (VT.isVector()) {
     SDOperand FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.Val) return FoldedVOp;
   }
@@ -1683,7 +1683,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
     ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
     
     if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
-        MVT::isInteger(LL.getValueType())) {
+        LL.getValueType().isInteger()) {
       // fold (X == 0) & (Y == 0) -> (X|Y == 0)
       if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
         SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
@@ -1709,7 +1709,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
       std::swap(RL, RR);
     }
     if (LL == RL && LR == RR) {
-      bool isInteger = MVT::isInteger(LL.getValueType());
+      bool isInteger = LL.getValueType().isInteger();
       ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
       if (Result != ISD::SETCC_INVALID)
         return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
@@ -1724,18 +1724,18 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
   
   // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
   // fold (and (sra)) -> (and (srl)) when possible.
-  if (!MVT::isVector(VT) &&
+  if (!VT.isVector() &&
       SimplifyDemandedBits(SDOperand(N, 0)))
     return SDOperand(N, 0);
   // fold (zext_inreg (extload x)) -> (zextload x)
   if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    MVT::ValueType EVT = LN0->getMemoryVT();
+    MVT EVT = LN0->getMemoryVT();
     // If we zero all the possible extended bits, then we can turn this into
     // a zextload if we are running before legalize or the operation is legal.
     unsigned BitWidth = N1.getValueSizeInBits();
     if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
-                                     BitWidth - MVT::getSizeInBits(EVT))) &&
+                                     BitWidth - EVT.getSizeInBits())) &&
         (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
       SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
                                          LN0->getBasePtr(), LN0->getSrcValue(),
@@ -1751,12 +1751,12 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
   if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
       N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    MVT::ValueType EVT = LN0->getMemoryVT();
+    MVT EVT = LN0->getMemoryVT();
     // If we zero all the possible extended bits, then we can turn this into
     // a zextload if we are running before legalize or the operation is legal.
     unsigned BitWidth = N1.getValueSizeInBits();
     if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
-                                     BitWidth - MVT::getSizeInBits(EVT))) &&
+                                     BitWidth - EVT.getSizeInBits())) &&
         (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
       SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
                                          LN0->getBasePtr(), LN0->getSrcValue(),
@@ -1775,7 +1775,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     if (LN0->getExtensionType() != ISD::SEXTLOAD &&
         LN0->isUnindexed() && N0.hasOneUse()) {
-      MVT::ValueType EVT, LoadedVT;
+      MVT EVT, LoadedVT;
       if (N1C->getAPIntValue() == 255)
         EVT = MVT::i8;
       else if (N1C->getAPIntValue() == 65535)
@@ -1788,12 +1788,12 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
       LoadedVT = LN0->getMemoryVT();
       if (EVT != MVT::Other && LoadedVT > EVT &&
           (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
-        MVT::ValueType PtrType = N0.getOperand(1).getValueType();
+        MVT PtrType = N0.getOperand(1).getValueType();
         // For big endian targets, we need to add an offset to the pointer to
         // load the correct bytes.  For little endian systems, we merely need to
         // read fewer bytes from the same pointer.
-        unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
-        unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
+        unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
+        unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
         unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
         unsigned Alignment = LN0->getAlignment();
         SDOperand NewPtr = LN0->getBasePtr();
@@ -1823,10 +1823,10 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
   SDOperand LL, LR, RL, RR, CC0, CC1;
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N1.getValueType();
+  MVT VT = N1.getValueType();
   
   // fold vector ops
-  if (MVT::isVector(VT)) {
+  if (VT.isVector()) {
     SDOperand FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.Val) return FoldedVOp;
   }
@@ -1868,7 +1868,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
     ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
     
     if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
-        MVT::isInteger(LL.getValueType())) {
+        LL.getValueType().isInteger()) {
       // fold (X != 0) | (Y != 0) -> (X|Y != 0)
       // fold (X <  0) | (Y <  0) -> (X|Y < 0)
       if (cast<ConstantSDNode>(LR)->isNullValue() && 
@@ -1892,7 +1892,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
       std::swap(RL, RR);
     }
     if (LL == RL && LR == RR) {
-      bool isInteger = MVT::isInteger(LL.getValueType());
+      bool isInteger = LL.getValueType().isInteger();
       ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
       if (Result != ISD::SETCC_INVALID)
         return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
@@ -1959,7 +1959,7 @@ static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
 // a rot[lr].
 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
   // Must be a legal type.  Expanded an promoted things won't work with rotates.
-  MVT::ValueType VT = LHS.getValueType();
+  MVT VT = LHS.getValueType();
   if (!TLI.isTypeLegal(VT)) return 0;
 
   // The target must have at least one rotate flavor.
@@ -1991,7 +1991,7 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
     std::swap(LHSMask , RHSMask );
   }
 
-  unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+  unsigned OpSizeInBits = VT.getSizeInBits();
   SDOperand LHSShiftArg = LHSShift.getOperand(0);
   SDOperand LHSShiftAmt = LHSShift.getOperand(1);
   SDOperand RHSShiftAmt = RHSShift.getOperand(1);
@@ -2115,10 +2115,10 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
   SDOperand LHS, RHS, CC;
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
   
   // fold vector ops
-  if (MVT::isVector(VT)) {
+  if (VT.isVector()) {
     SDOperand FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.Val) return FoldedVOp;
   }
@@ -2146,7 +2146,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
     return RXOR;
   // fold !(x cc y) -> (x !cc y)
   if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
-    bool isInt = MVT::isInteger(LHS.getValueType());
+    bool isInt = LHS.getValueType().isInteger();
     ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
                                                isInt);
     if (N0.getOpcode() == ISD::SETCC)
@@ -2205,12 +2205,12 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
   }
   // fold (xor x, x) -> 0
   if (N0 == N1) {
-    if (!MVT::isVector(VT)) {
+    if (!VT.isVector()) {
       return DAG.getConstant(0, VT);
     } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
       // Produce a vector of zeros.
-      SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
-      std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
+      SDOperand El = DAG.getConstant(0, VT.getVectorElementType());
+      std::vector<SDOperand> Ops(VT.getVectorNumElements(), El);
       return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
     }
   }
@@ -2222,7 +2222,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
   }
   
   // Simplify the expression using non-local knowledge.
-  if (!MVT::isVector(VT) &&
+  if (!VT.isVector() &&
       SimplifyDemandedBits(SDOperand(N, 0)))
     return SDOperand(N, 0);
   
@@ -2274,7 +2274,7 @@ SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
       !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
     return SDOperand();
   
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   
   // If this is a signed shift right, and the high bit is modified
   // by the logical operation, do not perform the transformation.
@@ -2305,8 +2305,8 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N0.getValueType();
-  unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+  MVT VT = N0.getValueType();
+  unsigned OpSizeInBits = VT.getSizeInBits();
   
   // fold (shl c1, c2) -> c1<<c2
   if (N0C && N1C)
@@ -2322,7 +2322,7 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) {
     return N0;
   // if (shl x, c) is known to be zero, return 0
   if (DAG.MaskedValueIsZero(SDOperand(N, 0),
-                            APInt::getAllOnesValue(MVT::getSizeInBits(VT))))
+                            APInt::getAllOnesValue(VT.getSizeInBits())))
     return DAG.getConstant(0, VT);
   if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
     return SDOperand(N, 0);
@@ -2364,7 +2364,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N0.getValueType();
+  MVT VT = N0.getValueType();
   
   // fold (sra c1, c2) -> c1>>c2
   if (N0C && N1C)
@@ -2376,7 +2376,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
   if (N0C && N0C->isAllOnesValue())
     return N0;
   // fold (sra x, c >= size(x)) -> undef
-  if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
+  if (N1C && N1C->getValue() >= VT.getSizeInBits())
     return DAG.getNode(ISD::UNDEF, VT);
   // fold (sra x, 0) -> x
   if (N1C && N1C->isNullValue())
@@ -2384,8 +2384,8 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
   // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
   // sext_inreg.
   if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
-    unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
-    MVT::ValueType EVT;
+    unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue();
+    MVT EVT;
     switch (LowBits) {
     default: EVT = MVT::Other; break;
     case  1: EVT = MVT::i1;    break;
@@ -2402,7 +2402,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
   if (N1C && N0.getOpcode() == ISD::SRA) {
     if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
       unsigned Sum = N1C->getValue() + C1->getValue();
-      if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
+      if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
       return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
                          DAG.getConstant(Sum, N1C->getValueType(0)));
     }
@@ -2418,8 +2418,9 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
     const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
     if (N01C && N1C) {
       // Determine what the truncate's result bitsize and type would be.
-      unsigned VTValSize = MVT::getSizeInBits(VT);
-      MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue());
+      unsigned VTValSize = VT.getSizeInBits();
+      MVT TruncVT =
+        MVT::getIntegerVT(VTValSize - N1C->getValue());
       // Determine the residual right-shift amount.
       unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
       
@@ -2458,8 +2459,8 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
   SDOperand N1 = N->getOperand(1);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  MVT::ValueType VT = N0.getValueType();
-  unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+  MVT VT = N0.getValueType();
+  unsigned OpSizeInBits = VT.getSizeInBits();
   
   // fold (srl c1, c2) -> c1 >>u c2
   if (N0C && N1C)
@@ -2492,8 +2493,8 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
   // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
   if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
     // Shifting in all undef bits?
-    MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
-    if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
+    MVT SmallVT = N0.getOperand(0).getValueType();
+    if (N1C->getValue() >= SmallVT.getSizeInBits())
       return DAG.getNode(ISD::UNDEF, VT);
 
     SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
@@ -2503,16 +2504,16 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
   
   // fold (srl (sra X, Y), 31) -> (srl X, 31).  This srl only looks at the sign
   // bit, which is unmodified by sra.
-  if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
+  if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) {
     if (N0.getOpcode() == ISD::SRA)
       return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
   }
   
   // fold (srl (ctlz x), "5") -> x  iff x has one bit set (the low bit).
   if (N1C && N0.getOpcode() == ISD::CTLZ && 
-      N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) {
+      N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
     APInt KnownZero, KnownOne;
-    APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
+    APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
     DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
     
     // If any of the input bits are KnownOne, then the input couldn't be all
@@ -2551,7 +2552,7 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
 
 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
 
   // fold (ctlz c1) -> c2
   if (isa<ConstantSDNode>(N0))
@@ -2561,7 +2562,7 @@ SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
 
 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   
   // fold (cttz c1) -> c2
   if (isa<ConstantSDNode>(N0))
@@ -2571,7 +2572,7 @@ SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
 
 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
-  MVT::ValueType VT = N->getValueType(0);
+  MVT VT = N->getValueType(0);
   
   // fold (ctpop c1) -> c2
   if (isa<ConstantSDNode>(N0))
@@ -2586,8 +2587,8 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
   ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
-  MVT::ValueType VT = N->getValueType(0);
-  MVT::ValueType VT0 = N0.getValueType();
+  MVT VT = N->getValueType(0);
+  MVT VT0 = N0.getValueType();
 
   // fold select C, X, X -> X
   if (N1 == N2)
@@ -2599,16 +2600,16 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
   if (N0C && N0C->isNullValue())
     return N2;
   // fold select C, 1, X -> C | X
-  if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1)
+  if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
     return DAG.getNode(ISD::OR, VT, N0, N2);
   // fold select C, 0, 1 -> ~C
-  if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
+  if (VT.isInteger() && VT0.isInteger() &&
       N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
     SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
     if (VT == VT0)
       return XORNode;
     AddToWorkList(XORNode.V