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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2011-05-28 00:13:01 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2011-05-28 00:13:01 +0000 |
| commit | 7bf114c1bd0390f4f485905d2fe9c7c6a048b8b7 (patch) | |
| tree | d9caff1363dc06d7c02bb22c9a16901ac9433321 /lib/CodeGen | |
| parent | de64aaf6c8ab3a170b2e5a5b0968595503b5aad4 (diff) | |
Fix the root cause of the bootstrap failure:
There was no way to check if a given register/mode pair was valid. We now return
an error code (-2) instead of asserting. If anyone thinks that an assert
at this point is really needed, we can autogen a hasValidDwarfRegNum instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132236 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 5617a0fa4b..dee6e53226 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -769,7 +769,7 @@ void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const { int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); for (const unsigned *SR = TRI->getSuperRegisters(MLoc.getReg()); - *SR && Reg == -1; ++SR) { + *SR && Reg < 0; ++SR) { Reg = TRI->getDwarfRegNum(*SR, false); // FIXME: Get the bit range this register uses of the superregister // so that we can produce a DW_OP_bit_piece |