diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-01-25 09:12:57 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-01-25 09:12:57 +0000 |
| commit | 3f23952404cd03a8ab934cedcef7916f52a796c0 (patch) | |
| tree | ecc739612209caa3f9a290d999313836081b4e8b /lib/CodeGen | |
| parent | d854b62afa9a9c3ee8c968199af0d94ed215e19e (diff) | |
If scheduler choice is the default (-sched=default), use target scheduling
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25599 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 7badd283a8..06a3b016de 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -59,8 +59,10 @@ namespace { ISHeuristic( "sched", cl::desc("Choose scheduling style"), - cl::init(noScheduling), + cl::init(defaultScheduling), cl::values( + clEnumValN(defaultScheduling, "default", + "Target preferred scheduling style"), clEnumValN(noScheduling, "none", "No scheduling: breadth first sequencing"), clEnumValN(simpleScheduling, "simple", @@ -69,7 +71,7 @@ namespace { clEnumValN(simpleNoItinScheduling, "simple-noitin", "Simple two pass scheduling: Same as simple " "except using generic latency"), - clEnumValN(listSchedulingBURR, "list-BURR", + clEnumValN(listSchedulingBURR, "list-burr", "Bottom up register reduction list scheduling"), clEnumValEnd)); } // namespace @@ -1772,6 +1774,12 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { switch (ISHeuristic) { default: assert(0 && "Unrecognized scheduling heuristic"); + case defaultScheduling: + if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) + SL = createSimpleDAGScheduler(noScheduling, DAG, BB); + else /* TargetLowering::SchedulingForRegPressure */ + SL = createBURRListDAGScheduler(DAG, BB); + break; case noScheduling: case simpleScheduling: case simpleNoItinScheduling: |