aboutsummaryrefslogtreecommitdiff
path: root/lib/CodeGen
diff options
context:
space:
mode:
authorReid Spencer <rspencer@reidspencer.com>2006-10-26 06:15:43 +0000
committerReid Spencer <rspencer@reidspencer.com>2006-10-26 06:15:43 +0000
commit1628cec4d7fce310d9cde0bcc73997e5a71692c4 (patch)
tree6dff5a70de8406b153e32fdd2d60c782d6202f63 /lib/CodeGen
parent7043d00750c558a518d08a638638ebe4d241f159 (diff)
For PR950:
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to have three division instructions: signed, unsigned, floating point. The bytecode and assembler are bacwards compatible, however. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31195 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp68
1 files changed, 44 insertions, 24 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7efc03efb0..9cf29436a5 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -499,28 +499,35 @@ public:
void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
- void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
+ void visitIntBinary(User &I, unsigned IntOp, unsigned VecOp);
+ void visitFPBinary(User &I, unsigned FPOp, unsigned VecOp);
void visitShift(User &I, unsigned Opcode);
void visitAdd(User &I) {
- visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
+ if (I.getType()->isFloatingPoint())
+ visitFPBinary(I, ISD::FADD, ISD::VADD);
+ else
+ visitIntBinary(I, ISD::ADD, ISD::VADD);
}
void visitSub(User &I);
- void visitMul(User &I) {
- visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
- }
- void visitDiv(User &I) {
- const Type *Ty = I.getType();
- visitBinary(I,
- Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
- Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
+ void visitMul(User &I) {
+ if (I.getType()->isFloatingPoint())
+ visitFPBinary(I, ISD::FMUL, ISD::VMUL);
+ else
+ visitIntBinary(I, ISD::MUL, ISD::VMUL);
}
+ void visitUDiv(User &I) { visitIntBinary(I, ISD::UDIV, ISD::VUDIV); }
+ void visitSDiv(User &I) { visitIntBinary(I, ISD::SDIV, ISD::VSDIV); }
+ void visitFDiv(User &I) { visitFPBinary(I, ISD::FDIV, ISD::VSDIV); }
void visitRem(User &I) {
const Type *Ty = I.getType();
- visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
- }
- void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
- void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
- void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
+ if (Ty->isFloatingPoint())
+ visitFPBinary(I, ISD::FREM, 0);
+ else
+ visitIntBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, 0);
+ }
+ void visitAnd(User &I) { visitIntBinary(I, ISD::AND, ISD::VAND); }
+ void visitOr (User &I) { visitIntBinary(I, ISD::OR, ISD::VOR); }
+ void visitXor(User &I) { visitIntBinary(I, ISD::XOR, ISD::VXOR); }
void visitShl(User &I) { visitShift(I, ISD::SHL); }
void visitShr(User &I) {
visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
@@ -1142,25 +1149,38 @@ void SelectionDAGLowering::visitSub(User &I) {
setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
return;
}
- }
- visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
+ visitFPBinary(I, ISD::FSUB, ISD::VSUB);
+ } else
+ visitIntBinary(I, ISD::SUB, ISD::VSUB);
}
-void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
- unsigned VecOp) {
+void
+SelectionDAGLowering::visitIntBinary(User &I, unsigned IntOp, unsigned VecOp) {
const Type *Ty = I.getType();
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
- if (Ty->isIntegral()) {
- setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
- } else if (Ty->isFloatingPoint()) {
- setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
+ if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
+ SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
+ SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
+ setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
} else {
- const PackedType *PTy = cast<PackedType>(Ty);
+ setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
+ }
+}
+
+void
+SelectionDAGLowering::visitFPBinary(User &I, unsigned FPOp, unsigned VecOp) {
+ const Type *Ty = I.getType();
+ SDOperand Op1 = getValue(I.getOperand(0));
+ SDOperand Op2 = getValue(I.getOperand(1));
+
+ if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
+ } else {
+ setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
}
}