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| author | Daniel Dunbar <daniel@zuster.org> | 2009-07-16 22:08:25 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2009-07-16 22:08:25 +0000 |
| commit | 24cd3c4711333ca1e07cbdb34475bccfeb762bb6 (patch) | |
| tree | 5b515b1f8b90413f97bb5fe01524ee0289b844fb /lib/CodeGen/VirtRegRewriter.cpp | |
| parent | efd280b4caf261b95551a317bb398a90d2e90011 (diff) | |
Fix inverted preprocessor conditional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76111 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/VirtRegRewriter.cpp')
| -rw-r--r-- | lib/CodeGen/VirtRegRewriter.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp index a859d80e1b..61ea80b3d9 100644 --- a/lib/CodeGen/VirtRegRewriter.cpp +++ b/lib/CodeGen/VirtRegRewriter.cpp @@ -491,7 +491,7 @@ static void ReMaterialize(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI, VirtRegMap &VRM) { MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg); -#ifdef NDEBUG +#ifndef NDEBUG const TargetInstrDesc &TID = ReMatDefMI->getDesc(); assert(TID.getNumDefs() != 1 && "Don't know how to remat instructions that define > 1 values!"); |