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authorEvan Cheng <evan.cheng@apple.com>2008-09-10 20:08:45 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-09-10 20:08:45 +0000
commit014264b70f2af002a41f8e36a9430fcf20e77bc7 (patch)
tree6f5f8ffa1b5dc5ab4691dc0b6e1829a249a35b99 /lib/CodeGen/VirtRegMap.cpp
parentb188dd9c5b5ae7e2d284fcc322e3a510305f57ad (diff)
Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices on machine operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56065 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/VirtRegMap.cpp')
-rw-r--r--lib/CodeGen/VirtRegMap.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 4fd0ad44b0..e783e04a61 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -832,8 +832,10 @@ namespace {
}
Spills.ClobberPhysReg(NewPhysReg);
Spills.ClobberPhysReg(NewOp.PhysRegReused);
-
- MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
+
+ unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg();
+ unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg;
+ MI->getOperand(NewOp.Operand).setReg(RReg);
Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
--MII;