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| author | Evan Cheng <evan.cheng@apple.com> | 2008-02-13 09:13:21 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-02-13 09:13:21 +0000 |
| commit | 9cec00e7f1dec7c3142d81c1256d198afa3718d3 (patch) | |
| tree | a68ab81935942de24464ff98883b26e4c7f4e581 /lib/CodeGen/TargetInstrInfoImpl.cpp | |
| parent | e984e504b5f3090ab270cbdab02638ac3a2afb21 (diff) | |
Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47058 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TargetInstrInfoImpl.cpp')
| -rw-r--r-- | lib/CodeGen/TargetInstrInfoImpl.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index 598b94af9c..4f6c1237e9 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -23,11 +23,9 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const { "This only knows how to commute register operands so far"); unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(2).getReg(); - MachineOperand &MO = MI->getOperand(0); - bool UpdateReg0 = MO.isReg() && MO.getReg() == Reg1; bool Reg1IsKill = MI->getOperand(1).isKill(); bool Reg2IsKill = MI->getOperand(2).isKill(); - if (UpdateReg0) { + if (MI->getOperand(0).getReg() == Reg1) { // Must be two address instruction! assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && "Expecting a two-address instruction!"); |