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authorEvan Cheng <evan.cheng@apple.com>2007-11-14 07:59:08 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-11-14 07:59:08 +0000
commitc498b0281fa81bc213ad1a1228664d480936c0e6 (patch)
tree9f5398569fe93f7e9c1f427daff5b051ecbcb14c /lib/CodeGen/SimpleRegisterCoalescing.cpp
parentf9572a4c2bcdec54ea70c7b14f4ac6b38cfdd70c (diff)
Clean up sub-register implementation by moving subReg information back to
MachineOperand auxInfo. Previous clunky implementation uses an external map to track sub-register uses. That works because register allocator uses a new virtual register for each spilled use. With interval splitting (coming soon), we may have multiple uses of the same register some of which are of using different sub-registers from others. It's too fragile to constantly update the information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44104 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SimpleRegisterCoalescing.cpp')
-rw-r--r--lib/CodeGen/SimpleRegisterCoalescing.cpp15
1 files changed, 9 insertions, 6 deletions
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 623d2951d0..b919e8a80b 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1387,6 +1387,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
r2rRevMap_.grow(RegMap->getLastVirtReg());
// Join (coalesce) intervals if requested.
+ IndexedMap<unsigned, VirtReg2IndexFunctor> RegSubIdxMap;
if (EnableJoining) {
joinIntervals();
DOUT << "********** INTERVALS POST JOINING **********\n";
@@ -1404,10 +1405,11 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
// Transfer sub-registers info to SSARegMap now that coalescing information
// is complete.
+ RegSubIdxMap.grow(mf_->getSSARegMap()->getLastVirtReg()+1);
while (!SubRegIdxes.empty()) {
std::pair<unsigned, unsigned> RI = SubRegIdxes.back();
SubRegIdxes.pop_back();
- mf_->getSSARegMap()->setIsSubRegister(RI.first, rep(RI.first), RI.second);
+ RegSubIdxMap[RI.first] = RI.second;
}
}
@@ -1448,12 +1450,13 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
// replace register with representative register
unsigned OrigReg = mop.getReg();
unsigned reg = rep(OrigReg);
- // Don't rewrite if it is a sub-register of a virtual register.
- if (!RegMap->isSubRegister(OrigReg))
+ unsigned SubIdx = RegSubIdxMap[OrigReg];
+ if (SubIdx && MRegisterInfo::isPhysicalRegister(reg))
+ mii->getOperand(i).setReg(mri_->getSubReg(reg, SubIdx));
+ else {
mii->getOperand(i).setReg(reg);
- else if (MRegisterInfo::isPhysicalRegister(reg))
- mii->getOperand(i).setReg(mri_->getSubReg(reg,
- RegMap->getSubRegisterIndex(OrigReg)));
+ mii->getOperand(i).setSubReg(SubIdx);
+ }
// Multiple uses of reg by the same instruction. It should not
// contribute to spill weight again.