diff options
| author | Owen Anderson <resistor@mac.com> | 2008-09-10 20:41:13 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2008-09-10 20:41:13 +0000 |
| commit | 369e98760bfdd6a72ef64929f3c560f80a4ffc92 (patch) | |
| tree | 219ac543568557c8844064ea36c0aeb737083eb9 /lib/CodeGen/SimpleRegisterCoalescing.cpp | |
| parent | 0586d91bb3e516d5826826522d9a90ed6ef74d86 (diff) | |
Fix a bug in the coalescer where it didn't check if a live interval existed before trying to manipulate it. This
was exposed by fast isel's handling of shifts on X86-64. With this, FreeBench/pcompress2 passes on X86-64 in fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56067 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SimpleRegisterCoalescing.cpp')
| -rw-r--r-- | lib/CodeGen/SimpleRegisterCoalescing.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index cca891d773..c6d4576e9c 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -464,7 +464,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, MachineOperand &MO = CopyMI->getOperand(i); if (MO.isReg() && MO.isImplicit()) NewMI->addOperand(MO); - if (MO.isDef()) { + if (MO.isDef() && li_->hasInterval(MO.getReg())) { unsigned Reg = MO.getReg(); DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx); if (DLR && DLR->valno->copy == CopyMI) |