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| author | Dan Gohman <gohman@apple.com> | 2010-02-10 16:03:48 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2010-02-10 16:03:48 +0000 |
| commit | f451cb870efcf9e0302d25ed05f4cac6bb494e42 (patch) | |
| tree | f614bd15d6f3e0b944c58469b235dafc3e693747 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | c056baed8704bd715ee58e5dfe724c255e68abbd (diff) | |
Fix "the the" and similar typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f923927c43..d74ec7e2e5 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2366,7 +2366,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, E = RI->regclass_end(); RCI != E; ++RCI) { const TargetRegisterClass *RC = *RCI; - // If none of the the value types for this register class are valid, we + // If none of the value types for this register class are valid, we // can't use it. For example, 64-bit reg classes on 32-bit targets. bool isLegal = false; for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); |