diff options
| author | Patrik Hagglund <patrik.h.hagglund@ericsson.com> | 2012-12-19 11:48:16 +0000 |
|---|---|---|
| committer | Patrik Hagglund <patrik.h.hagglund@ericsson.com> | 2012-12-19 11:48:16 +0000 |
| commit | dfcf33a287d1756721f1f735af687595ce2f5a21 (patch) | |
| tree | 2806c1ff5884e04d35d70fc83836b541d0a7c820 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | ff01277841b824128c74cdb66f74d8082d75e3f6 (diff) | |
Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170535 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 52867bd18a..94914d3195 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -688,7 +688,7 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, if (!isPowerOf2_32(NewVTSize)) NewVTSize = NextPowerOf2(NewVTSize); - EVT DestVT = TLI->getRegisterType(NewVT); + MVT DestVT = TLI->getRegisterType(NewVT); RegisterVT = DestVT; if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); @@ -870,7 +870,7 @@ void TargetLowering::computeRegisterProperties() { NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, RegisterVT, this); - RegisterTypeForVT[i] = RegisterVT; + RegisterTypeForVT[i] = RegisterVT.getSimpleVT(); MVT NVT = VT.getPow2VectorType(); if (NVT == VT) { @@ -1011,13 +1011,13 @@ void llvm::GetReturnInfo(Type* ReturnType, Attribute attr, // conventions. The frontend should mark functions whose return values // require promoting with signext or zeroext attributes. if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { - EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); + MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); if (VT.bitsLT(MinVT)) VT = MinVT; } unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); - EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); + MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); // 'inreg' on function refers to return value ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); |