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| author | Duncan Sands <baldrick@free.fr> | 2008-07-11 16:52:29 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2008-07-11 16:52:29 +0000 |
| commit | dddc6291fb5274282a20d5923b50535d456d34a4 (patch) | |
| tree | 6e83f3cbdb0c08fa48dbc6944d595a1b27c6cf80 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 7d9843fc374296e85769c820ec9c333be1e74c0a (diff) | |
Add support for 128 bit shifts and 32 bit shifts
on 16 bit machines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53458 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index ee72012133..4a2a0c0390 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -31,10 +31,13 @@ using namespace llvm; static void InitLibcallNames(const char **Names) { Names[RTLIB::SHL_I32] = "__ashlsi3"; Names[RTLIB::SHL_I64] = "__ashldi3"; + Names[RTLIB::SHL_I128] = "__ashlti3"; Names[RTLIB::SRL_I32] = "__lshrsi3"; Names[RTLIB::SRL_I64] = "__lshrdi3"; + Names[RTLIB::SRL_I128] = "__lshrti3"; Names[RTLIB::SRA_I32] = "__ashrsi3"; Names[RTLIB::SRA_I64] = "__ashrdi3"; + Names[RTLIB::SRA_I128] = "__ashrti3"; Names[RTLIB::MUL_I32] = "__mulsi3"; Names[RTLIB::MUL_I64] = "__muldi3"; Names[RTLIB::MUL_I128] = "__multi3"; |