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authorDaniel Dunbar <daniel@zuster.org>2010-02-24 17:05:47 +0000
committerDaniel Dunbar <daniel@zuster.org>2010-02-24 17:05:47 +0000
commitcfe30effbb952ae5b49a01de8329e3a2c14bad75 (patch)
tree1aadf15226e7242aa2984e90448bbcb9e3a80a07 /lib/CodeGen/SelectionDAG/TargetLowering.cpp
parent6d8f2ca646bc283c31f48b6816d5194c836dfec6 (diff)
Speculatively revert r97011, "Re-apply 96540 and 96556 with fixes.", again in
the hopes of fixing PPC bootstrap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97040 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp40
1 files changed, 7 insertions, 33 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 96d4e20ee2..e88af4f3e0 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1775,7 +1775,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
break; // todo, be more careful with signed comparisons
}
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
- (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
+ (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
EVT ExtDstTy = N0.getValueType();
@@ -1809,21 +1809,22 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Cond);
} else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
+
// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
- if (N0.getOpcode() == ISD::SETCC &&
- isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
+ if (N0.getOpcode() == ISD::SETCC) {
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
if (TrueWhenTrue)
- return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
+ return N0;
+
// Invert the condition.
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
CC = ISD::getSetCCInverse(CC,
N0.getOperand(0).getValueType().isInteger());
return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
}
-
+
if ((N0.getOpcode() == ISD::XOR ||
- (N0.getOpcode() == ISD::AND &&
+ (N0.getOpcode() == ISD::AND &&
N0.getOperand(0).getOpcode() == ISD::XOR &&
N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
isa<ConstantSDNode>(N0.getOperand(1)) &&
@@ -1846,36 +1847,9 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
N0.getOperand(0).getOperand(0),
N0.getOperand(1));
}
-
return DAG.getSetCC(dl, VT, Val, N1,
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
}
- } else if (N1C->getAPIntValue() == 1) {
- SDValue Op0 = N0;
- if (Op0.getOpcode() == ISD::TRUNCATE)
- Op0 = Op0.getOperand(0);
-
- if ((Op0.getOpcode() == ISD::XOR || Op0.getOpcode() == ISD::AND) &&
- Op0.getOperand(0).getOpcode() == ISD::SETCC &&
- Op0.getOperand(1).getOpcode() == ISD::SETCC) {
- // (and (setcc), (setcc)) == / != 1 -> (setcc) == / != (setcc)
- // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
- if (Op0.getOpcode() == ISD::XOR)
- Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
- return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
- Cond);
- } else if (Op0.getOpcode() == ISD::AND &&
- isa<ConstantSDNode>(Op0.getOperand(1)) &&
- cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
- // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
- if (Op0.getValueType() != VT)
- Op0 = DAG.getNode(ISD::AND, dl, VT,
- DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
- DAG.getConstant(1, VT));
- return DAG.getSetCC(dl, VT, Op0,
- DAG.getConstant(0, Op0.getValueType()),
- Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
- }
}
}