diff options
author | Jim Laskey <jlaskey@mac.com> | 2006-06-13 13:08:58 +0000 |
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committer | Jim Laskey <jlaskey@mac.com> | 2006-06-13 13:08:58 +0000 |
commit | 9bfa2dcff6c341814c18703d6760c3645bcc14e9 (patch) | |
tree | 128e16634b70869840c70f56efa727c452fb4cb0 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
parent | 004fb92615b23e661da9d0bfd883296094b8b777 (diff) |
TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28765 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f4e807009b..6c59a0913d 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -780,12 +780,14 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, case ISD::SHL: // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { + uint64_t LowBits = (1ULL << SA->getValue())-1; Mask >>= SA->getValue(); ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); KnownZero <<= SA->getValue(); KnownOne <<= SA->getValue(); - KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. + KnownZero |= LowBits; // low bits known zero + KnownOne &= ~LowBits; // and known not to be one. } return; case ISD::SRL: @@ -798,7 +800,8 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); KnownZero >>= SA->getValue(); KnownOne >>= SA->getValue(); - KnownZero |= HighBits; // high bits known zero. + KnownZero |= HighBits; // high bits known zero + KnownOne &= ~HighBits; // and known not to be one. } return; case ISD::SRA: @@ -815,10 +818,12 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1); SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. - if (KnownZero & SignBit) { // New bits are known zero. - KnownZero |= HighBits; - } else if (KnownOne & SignBit) { // New bits are known one. - KnownOne |= HighBits; + if (KnownZero & SignBit) { + KnownZero |= HighBits; // New bits are known zero + KnownOne &= ~HighBits; // and known not to be one. + } else if (KnownOne & SignBit) { + KnownOne |= HighBits; // New bits are known one + KnownZero &= ~HighBits; // and known not to be zero. } } return; |