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| author | Jeff Cohen <jeffc@jolt-lang.org> | 2006-02-17 02:12:18 +0000 |
|---|---|---|
| committer | Jeff Cohen <jeffc@jolt-lang.org> | 2006-02-17 02:12:18 +0000 |
| commit | 5755b17044b5929b89f06f6f8d19e9ccd4d6c0c9 (patch) | |
| tree | 6103d7c4402773ab7f043a3da4c55251648f8209 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | ddc0022c6f354e3ef1ad86b7c43f2482e5bd30aa (diff) | |
Fix bug noticed by VC++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26252 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 71c7d90f7d..a48e907490 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -243,9 +243,9 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, // If all of the demanded bits are known zero on one side, return the other. // These bits cannot contribute to the result of the 'or'. - if ((DemandedMask & ~KnownOne2 & KnownZero) == DemandedMask & ~KnownOne2) + if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) return TLO.CombineTo(Op, Op.getOperand(0)); - if ((DemandedMask & ~KnownOne & KnownZero2) == DemandedMask & ~KnownOne) + if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) return TLO.CombineTo(Op, Op.getOperand(1)); // If all of the potentially set bits on one side are known to be set on // the other side, just use the 'other' side. |