diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-10-11 07:10:22 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-10-11 07:10:22 +0000 |
| commit | 2e49f090f9656af7d5ed4d5c4e9fa26af59c7233 (patch) | |
| tree | b6a464549ca50d08a4889b08254c998125998deb /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 27b1bb999b33d4b54308f51e6e03bcc0dda51a21 (diff) | |
Naming consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30878 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 73cefc4e38..0183678464 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -555,7 +555,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, case ISD::LOAD: { if (ISD::isZEXTLoad(Op.Val)) { LoadSDNode *LD = cast<LoadSDNode>(Op); - MVT::ValueType VT = LD->getLoadVT(); + MVT::ValueType VT = LD->getLoadedVT(); KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; } break; @@ -896,7 +896,7 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, case ISD::LOAD: { if (ISD::isZEXTLoad(Op.Val)) { LoadSDNode *LD = cast<LoadSDNode>(Op); - MVT::ValueType VT = LD->getLoadVT(); + MVT::ValueType VT = LD->getLoadedVT(); KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; } return; @@ -1205,10 +1205,10 @@ unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ switch (ExtType) { default: break; case ISD::SEXTLOAD: // '17' bits known - Tmp = MVT::getSizeInBits(LD->getLoadVT()); + Tmp = MVT::getSizeInBits(LD->getLoadedVT()); return VTBits-Tmp+1; case ISD::ZEXTLOAD: // '16' bits known - Tmp = MVT::getSizeInBits(LD->getLoadVT()); + Tmp = MVT::getSizeInBits(LD->getLoadedVT()); return VTBits-Tmp; } } |