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authorChris Lattner <sabre@nondot.org>2007-02-24 02:09:29 +0000
committerChris Lattner <sabre@nondot.org>2007-02-24 02:09:29 +0000
commit01ca65b23e31a1dfac702cef9a2fc963347a3f71 (patch)
tree46e5be70d57d84e3f7e3c2b45e097f17933e7585 /lib/CodeGen/SelectionDAG/TargetLowering.cpp
parent8c0261b5909aed92beab0fa6781c98d31f63f945 (diff)
Fix CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll and PR1219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34551 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 623d9a1c0f..073588cd12 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1459,11 +1459,11 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
case ISD::SETGT:
case ISD::SETGE:
// True if the sign bit of C1 is set.
- return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
+ return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
case ISD::SETLT:
case ISD::SETLE:
// True if the sign bit of C1 isn't set.
- return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
+ return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
default:
break;
}