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| author | Chris Lattner <sabre@nondot.org> | 2006-03-01 04:52:55 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-01 04:52:55 +0000 |
| commit | 00ffed0468ad406062b7c08c2ff46d79d2d1be4d (patch) | |
| tree | 4e2476c955a8a38cd672cb6efa66a86fdfadfd29 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 5750df9d695bf5aea6d672d00fdfb4243984fd38 (diff) | |
Add interfaces for targets to provide target-specific dag combiner optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26442 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index d170d6c292..2ba754289c 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -30,6 +30,8 @@ TargetLowering::TargetLowering(TargetMachine &tm) ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType()); ShiftAmtHandling = Undefined; memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); + memset(TargetDAGCombineArray, 0, + sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0])); maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; allowUnalignedMemoryAccesses = false; UseUnderscoreSetJmpLongJmp = false; @@ -916,6 +918,12 @@ void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, KnownOne = 0; } +SDOperand TargetLowering:: +PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { + // Default implementation: no optimization. + return SDOperand(); +} + //===----------------------------------------------------------------------===// // Inline Assembler Implementation Methods //===----------------------------------------------------------------------===// |