Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from

TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 2 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index bc29cbc66a..cce0a3254a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5026,7 +5026,7 @@ bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
   // Otherwise, the DAG Combiner may have proven that the value coming in is
   // either already zero or is not demanded.  Check for known zero input bits.
   uint64_t NeededMask = DesiredMask & ~ActualMask;
-  if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
+  if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
     return true;
   
   // TODO: check to see if missing bits are just not demanded.
@@ -5057,7 +5057,7 @@ bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
   uint64_t NeededMask = DesiredMask & ~ActualMask;
   
   uint64_t KnownZero, KnownOne;
-  getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
+  CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
   
   // If all the missing bits in the or are already known to be set, match!
   if ((NeededMask & KnownOne) == NeededMask)